1. Field of the Invention
The present invention relates to nonvolatile memory devices and, more particularly, to arrangements of nonvolatile memory devices with each memory level stacked level by level above a semiconductor substrate.
2. Description of Related Art
A nonvolatile semiconductor memory device is typically designed to securely hold data even when power is lost or removed from the memory device. Several types of nonvolatile memory devices have been proposed in the related art, examples of which include U.S. Pat. No. 4,489,478 (the '478 patent) to Sakurai, U.S. Pat. No. 5,441,907 (the '907 patent) to Sung et al., U.S. Pat. No. 5,536,968 to Crafts et al. (the '968 patent), U.S. Pat. No. 5,565,703 to Chang (the '703 patent), U.S. Pat. No. 5,835,396 (the '396 patent) to Zhang, and U.S. Pat. No. 6,034,882 (the '882 patent) to Johnson et al.
The nonvolatile memory devices taught by the '907 and '968 patents appear to suffer from a disadvantage wherein the number of nonvolatile devices per unit area of semiconductor substrate is limited by their arrangement in a two-dimensional structure. The device taught by the '907 patent does not appear to be electrically programmable. Furthermore, the polysilicon fuse array structure disclosed in the '968 patent has the disadvantage that the fuse arrays appear to require relatively large separations between adjacent elements, and the vertical anti-fuse structures described in the '703, 396 and '882 patents appear to require substantial areas of the semiconductor floor plan.
Needs thus exist in the related art for nonvolatile memory devices that can be implemented with an increased number of nonvolatile memory devices per unit area of semiconductor substrate, that are electrically programmable at sufficiently high programming rates and that occupy a reduced area of semiconductor floor plan.